1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, the improvement of pad arrangements of the semiconductor device.
2. Description of the Related Art
Generally, pad arrangements depend on types of semiconductor packages. For example, in a tape carrier package (TCP) specific semiconductor chip, pads are needed to he located in a linear arrangement in consideration of the mounting restriction on a tape. For example, the spacing between the pads is relatively small, for example, about 70 .mu.m. Also, in a chip-on-glass (COG) specific chip, pads are not needed to be located in a linear arrangement, and are actually located in a staggered (zigzagged) arrangement. For example, the spacing between the pads is relatively large, for example, about 150 .mu.m. This will be explained later in detail.
A semiconductor chip may be designed for both TCP and COG packages. In this case, however, since pads of a linear arrangement whose spacing is relatively large are adopted, the chip is deteriorated in terms of integration. This will also be explained later in detail.
Note that, in the prior art, it is known that a plurality of first pads and a plurality of second pads are arranged linearly in a row, and one of the first pads and one of the second pads are capable of receiving the same signal (see: JP-A-60-98652). Also in this case, however, the size of the chip is increased, and accordingly, the chip is deteriorated in terms of integration.